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Ajeya NaithaniAssistant Professor in Computer Architecture |
I am an assistant professor in the Electronic Systems group of the Department of Electrical Engineering at Eindhoven University of Technology (TU/e). Prior to joining TU/e, I was first a PhD student (graduated 2019) and then a postdoctoral researcher at Ghent University, in the research group of Professor Lieven Eeckhout. I received my MS degree in computer science from the University of Arizona in 2011.
Research
My research interests include the area of computer architecture with an emphasis on designing novel techniques to improve performance, energy efficiency, reliability, and security on modern processors.
Awards
Selection of Decoupled Vector Runahead as an IEEE Micro Top Pick 2023
Best Paper Award, MICRO 2023
Selection of Vector Runahead as an IEEE Micro Top Pick 2021
Program Committees
MICRO: 2024
HPCA: 2025 (ERC)
PACT: 2024
ISPASS: 2024
IISWC: 2023
Publications
2024
Scalar Vector Runahead
Jaime Roelandts, Ajeya Naithani, Sam Ainsworth, Timothy M. Jones, and Lieven Eeckhout
ACM/IEEE International Symposium on Microarchitecture (MICRO)| To appear
Decoupled Vector Runahead for Prefetching Nested Memory-Access Chains
Ajeya Naithani, Jaime Roelandts, Sam Ainsworth, Timothy M. Jones, and Lieven Eeckhout
IEEE Micro, Special Issue on Top Picks from 2023 Microarchitecture Conferences|PDF
2023
Decoupled Vector Runahead
Ajeya Naithani, Jaime Roelandts, Sam Ainsworth, Timothy M. Jones, and Lieven Eeckhout
ACM/IEEE International Symposium on Microarchitecture (MICRO)|PDF
Best Paper Award
Selected as an IEEE Micro Top Pick from 2023 for "most significant paper in computer architecture based on novelty and long-term impact"
2022
Vector Runahead for Indirect Memory Accesses
Ajeya Naithani, Sam Ainsworth, Timothy M. Jones, and Lieven Eeckhout
IEEE Micro, Special Issue on Top Picks from 2021 Microarchitecture Conferences|PDF
Reliability-Aware Runahead
Ajeya Naithani, and Lieven Eeckhout
IEEE International Symposium on High-Performance Computer Architecture (HPCA)|PDF
The Forward Slice Core: A High-Performance, Yet Low-Complexity Microarchitecture
Kartik Lakshminarasimhan, Ajeya Naithani, Josue Feliu Perez, and Lieven Eeckhout
ACM Transactions on Architecture and Code Optimization (TACO)|PDF
2021
Vector Runahead
Ajeya Naithani, Sam Ainsworth, Timothy M. Jones, and Lieven Eeckhout
ACM/IEEE International Symposium on Computer Architecture (ISCA)|PDF
Selected as an IEEE Micro Top Pick from 2021 for "most significant paper in computer architecture based on novelty and long-term impact"
VMT: Virtualized Multi-Threading for Accelerating Graph Workloads on Commodity Processors
Josue Feliu Perez, Ajeya Naithani, Julio Sahuquillo, Salvador Petit, Moinuddin K Qureshi, and Lieven Eeckhout
IEEE Transaction on Computers (TC)|PDF
2020
The Forward Slice Core Microarchitecture
Kartik Lakshminarasimhan, Ajeya Naithani, Josue Feliu Perez, and Lieven Eeckhout
ACM International Conference on Parallel Architectures and Compilation Techniques (PACT)|PDF
Precise Runahead Execution
Ajeya Naithani, Josue Feliu Perez, Almutaz Adileh, and Lieven Eeckhout
IEEE International Symposium on High-Performance Computer Architecture (HPCA)|PDF
2019
Improving Soft Error Reliability in Modern Processors
Ajeya Naithani
PhD Dissertation|PDF
Precise Runahead Execution
Ajeya Naithani, Josue Feliu Perez, Almutaz Adileh, and Lieven Eeckhout
IEEE Computer Architecture Letters (CAL)|PDF
2018
Optimizing Soft Error Reliability through Scheduling on Heterogeneous Multicore Processors
Ajeya Naithani, Stijn Eyerman, and Lieven Eeckhout
IEEE Transaction on Computers (TC)|PDF
2017
Reliability-Aware Scheduling on Heterogeneous Multicore Processors
Ajeya Naithani, Stijn Eyerman, and Lieven Eeckhout
IEEE International Symposium on High Performance Computer Architecture (HPCA) |PDF
Patents
CPU with Multiple Instruction Queues
Lieven Eeckhout, Kartik Lakshminarasimhan, and Ajeya Naithani
European Patent Application Number 20199592.5 (Pending), October 1, 2020